Shenzhen Hiner Technology Co.,LTD

Manufacturer from China
Verified Supplier
5 Years
Home / Products / Jedec IC Trays /

ESD Plastic JEDEC Standard Matrix Tray For IC Packaging

Contact Now
Shenzhen Hiner Technology Co.,LTD
Visit Website
City:shenzhen
Province/State:guangdong
Country/Region:china
Contact Person:MsRainbow Zhu
Contact Now

ESD Plastic JEDEC Standard Matrix Tray For IC Packaging

Ask Latest Price
Video Channel
Brand Name :Hiner-pack
Model Number :HN21085
Certification :ISO 9001 ROHS SGS
Place of Origin :Made In China
MOQ :1000 pcs
Price :$1.35~$2.38(Prices are determined according to different incoterms and quantities)
Payment Terms :T/T
Supply Ability :The capacity is between 2500PCS~3000PCS/per day
Delivery Time :5~8 working days
Packaging Details :80~100pcs/per carton, Weight about 12~16kg/per carton, Carton size is 35*30*30mm
Material :PC
Color :Black
Property :Non-ESD
Surface resistance :1.0x10E4~1.0x10E11Ω
Flatness :Less than 0.76mm
Clean Class :General and ultrasonic cleaning
Incoterms :EXW, FOB, CIF, DDU, DDP
Customized service :Support standard and non-standard,precision machining
Injection mold :Customized case need (Lead time 25~30Days, Mold Life Span: 300,000 times.)
more
Contact Now

Add to Cart

Find Similar Videos
View Product Description

JEDEC Standard Plastic JEDEC Matrix Trays for IC Packaging

Perfect for SMT, IC testing, and packaging lines, our trays are compatible with most JEDEC tray handlers and stackers.


JEDEC tray is the packaging tray used by the enterprise for its chip packaging test. Because the IC chip is small and thin, the enterprise will generally take external protection to avoid scratches and damage.


JEDEC Matrix Tray, which is a satisfactory storage of electronic components chip tray used by semiconductor sealing test enterprises for their chip packaging test. The bottom surface of the tray is flush and is made of mixed material. This mixed material gives the material excellent heat resistance, strength, flame retardant, and other properties. The base of the tray is set with fine, tight mesh slots. It not only effectively prevents damage to the product caused by vibration, but also has anti-static, pollution-free, and anti-corrosion characteristics.

Application:

Electronic component factories, SMT Surfacing factories, Optical industry, Military Industry

Technical Parameters:

Brand Hiner-pack Outline Line Size 322.6*135.9*7.62mm
Model HN21085 Cavity Size ∅33*2.93mm
Package Type IC Component Matrix QTY 14*6=84PCS
Material PC Flatness MAX 0.76mm
Color Black (can be customized) Service Accept OEM, ODM
Resistance 1.0x10e4-1.0x10e11Ω Certificate RoHS

Reference to the temperature resistance of different materials with the JEDEC Tray:

Material Bake Temperature Surface Resistance
PPE Bake 125°C~Max 150°C 1.0*10E4Ω~1.0*10E11Ω
MPPO+Carbon Fiber Bake 125°C~Max 150°C 1.0*10E4Ω~1.0*10E11Ω
MPPO+Carbon Powder Bake 125°C~Max 150°C 1.0*10E4Ω~1.0*10E11Ω
MPPO+Glass Fiber Bake 125°C~Max 150°C 1.0*10E4Ω~1.0*10E11Ω
PEI+Carbon Fiber Max 180°C 1.0*10E4Ω~1.0*10E11Ω
IDP Color 85°C 1.0*10E6Ω~1.0*10E10Ω
Color, temperature, and other special requirements can be customized

ESD Plastic JEDEC Standard Matrix Tray For IC Packaging

FAQ:

Q1. Do your products get any certificates?
Yes, CE for the EU market, FDA for the USA market.
Q2.Can you do the design for us?
Yes. We have a professional team having rich experience in designing and manufacturing. Just tell us your ideas and we will help to carry out your ideas into perfect fact. It does not matter if you do not have some one to complete files. Send us high resolution images, your logo and text and tell us how you would like to arrange them. We will send you finished files for confirmation.
Q3: Could you put my logo in our product?
Yes, we can put your logo in our product, show us your logo firstly please.

Q4: When can we get the samples?
We can send you them right now if you are interested in something we have stock, and customize.The project depending on the specific time.

ESD Plastic JEDEC Standard Matrix Tray For IC Packaging

Inquiry Cart 0